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Thread starter Space Varmint Start date Sep 1, Space Varmint New Member Sep 1, Is the Qd output the divide by 10 frequency? I have used decade counters using the “carry output” but I don’t have one hooked up right now. If I remember correctly it is an asynchronous signal. Would it be suitable to run into another decade counter and get valid divide by ten BCD on all Q outputs if I run Qd from one into the clock of another?
BrownOut Banned Sep 1, Post the part number of the part you’re using, and any data you have on it. I intend to use the 74hc data sheet: It appears, from looking at the datasheet, that indeed Q4 is a divide by 10 output, when the chip is configured for a decade counter. I don’t know what that other configuration is. I think I got it now.
Well those pins are not on the pinout. Mikebits Well-Known Member Sep 1, Q0 would be Qa.
Did you derive that from the data sheet? It was not a stupid question.
MCHC Datasheet(PDF) – ON Semiconductor
You’re maybe confusing this with the term “symmetrical”. The Qd output of dataseet any counter that is not a pure binary counter is often non-symmetrical, that is, the output is not a perfect square wave.
The TTL counter is such a beast. However, if you don’t use the outputs to drive a display, you can switch the divide-by-2 section datasehet the divide-by-five section so that the divide-by-two section is last in each decade chain and then you WILL have a symmetrical output. But the larger counter chips that incorporate several like stages do not have access to the divide-by-two stages so you can’t do that.
BrownOut Banned Sep 2, So that’s the purpose of the “other” mode. But if the OP is only interested in clocking a subsequent stage, symmetrical output isn’t required. Thanks for that description. Space Varmint New Member Sep 3, You do have to be careful with counters. If they’re ripple counters, they’ll ripple in cascade. And just because a counter is a synchronous counter doesn’t mean 74yc390 it’s synchronous in every sense or will be synchronous in cascade.
For instance, the synchronous decade counter is synchronous in its counting only. Parallel load and reset are asynchronous operations.
And when you want to cascade them, the various stages will be rippled even though within each stage it’s synchronous. You have to use a series counter to get full synchronous operation in all phases.
But you’ll still potentially have a non-symmetrical Qd output if it’s not a straight binary counter. As mentioned, it takes a pretty special application of a counter such that you require a symmetrical Qd output. Using a Qd output as the gate input for a frequency counter would be a bad idea! I noticed your signature.
That wasn’t a billed response was it?